This application claims priority under 35 U.S.C. § 119 (a) on Patent Application No. 2004-312520 filed in Japan on Oct. 27, 2004, the entire contents of which are hereby incorporated by reference.
The present invention relates to a method for producing a multilayer printed wiring board that improves the reliability of through-hole conductor formed on a multilayer printed wiring board, a multilayer printed wiring board, and an electronic device using such a multilayer printed wiring board.
FIGS. 13 and 14 are cross-sectional views in a process for explaining a multilayer printed wiring board of Conventional example 1 and a method for producing the same.
FIG. 13 shows a base material of a multilayer printed wiring board of Conventional example 1. For the base material of the multilayer printed wiring board, a commercially available laminate having copper coating on both its sides, more specifically a laminate having a copper foil as a metal foil 102 laminated on each side of a resin plate 101 serving as a core material, is used. A through-hole 103 (see FIG. 14) is formed on the base material with a drill or the like, followed by application of an appropriate plating pretreatment.
FIG. 14 shows a state in which the laminate having copper coating on both its sides for a multilayer printed wiring board whose entire surface has been subjected to panel plating after the plating pretreatment performed in FIG. 13. The panel plating is a plating process to form a metal layer (a panel plating layer 104 and a panel-plated through-hole conductor 104a) on the entire surface of the multilayer printed wiring board (laminate having copper coating on both its sides) through electroless plating or electrolytic plating. The metal plating is usually performed using the same metal as the metal foil 102.
Subsequent to application of the panel plating, the multilayer printed wiring board is formed by forming an etching resist on the surface of the panel plating layer 104 and patterning the panel plating layer 104 and the metal foil 102 so that a conductor pattern that corresponds to specific circuit wiring is formed.
In addition to Conventional example 1 described above, Conventional examples 2 and 3 as follows have also been known.
As Conventional example 2, a method is proposed in which a desired pattern (conductor pattern) including a land portion for forming wiring around a through-hole portion is formed on the surface of a copper-coated laminate substrate, and then a resist is formed on the portions other than the through-hole portion and the land portion before a hole is opened so as to form the through-hole portion (for example, JP S60-43893A (hereinafter referred to as Patent document 1) and Japanese Patent No. 3048360 (hereinafter referred to as Patent document 2). This method requires an additional plating process since a through-hole conductor is formed by separately performing a plating process exclusively to the through-hole portion. In addition, as the land portion becomes smaller, positioning becomes more difficult.
As Conventional example 3, a method is proposed in which a through-hole conductor is formed by forming a desirable circuit conductor (conductor pattern) on the surface of an insulating substrate, then forming a protective film on the entire surface, forming a hole (through-hole), and removing the protective film from around the through-hole (for example, see JP H8-34340B). This method also entails the same problems as Patent documents 1 and 2.
As the size reduction and sophistication level of electronic devices advance, a demand for increased wiring density on a wiring board has become stronger. Responding to such a demand, the number of conductor layers on a wiring board shows an increase in trend. Meanwhile, there has also been a strong demand for cost reduction for wiring boards, and a demand for reduced number of conductor layers to reduce wiring board cost has also been strong. With these backgrounds, the line width of wiring patterns (conductor patterns) has kept decreasing in order to achieve a higher wiring density. This tendency is especially significant in a conductor pattern on the outer-most layer of wiring boards.
When forming a conductor pattern using a conventional etching method, it is difficult to achieve a fine conductor pattern beyond a certain point due to an issue of aspect ratio between the line width and film thickness of a conductor pattern. For example, as mentioned in Conventional example 1, the film thickness of a conductor in a layer for forming a conductor pattern (metal foil and panel plating layer) is a sum of the film thickness of a metal foil layered on a multilayer printed wiring board as the base material and the film thickness of a panel plating layer formed through panel plating, which results in 50 μm or more in normal constructions.
In addition, when forming a conductor pattern through etching, it is difficult to change the etching speed ratio between the depth direction and plane direction of the conductor pattern. The ratio between the minimum line spacing (width between conductor patterns) and film thickness of a conductor (film thickness of a conductor pattern) that can be produced by patterning is close to 1:1.
In general, the line width of a conductor pattern and the conductor pattern spacing are designed so that the ratio is close to 1:1. For this reason, it has not been easy to form a conductor pattern with a line width smaller than the film thickness of the conductor pattern.
Consequently, when a finer conductor pattern with a smaller line width is desired, a generally selected method is to reduce the film thickness of a panel plating layer or the film thickness of a metal foil, which is layered on the multilayer printed wiring board as the base material.
The film thickness of a panel plating layer is equal to the film thickness of a through-hole conductor. However, the film thickness of a through-hole conductor can become smaller than the film thickness of a panel plating layer depending on conditions such as the state of the wall surface of the through-hole and the flow of plating fluid, and often varies due to unstable deposition of a plating metal. Accordingly, the film thickness of a panel plating layer cannot be reduced too much, in view of the heat stress to be applied during the use of the multilayer printed wiring board and at the time of mounting electronic components, reliability in a long-term use, an increase in the conductive resistance of through-hole conductor and others, and therefore a conductor pattern with a small line width cannot be formed.
In addition, although it is possible to reduce the film thickness of the metal foil to some extent, there are problems in that the production cost increases to form thin metal foils, and in that handling of the metal foils is more difficult because of their small thickness, for example, a surface treatment prior to formation of a panel plating layer (pretreatment for plating) is performed with difficulty.
Furthermore, when the film thickness of the panel plating layer is reduced relative to the film thickness of the metal foil, the film thickness of the through-hole conductor (panel plating layer) can become particularly thin around the opening of the through-hole (shoulder area of the land portion of the through-hole conductor which achieves conductivity between the through-hole conductor and the metal foil), which could result in susceptibility to thermal shock. In other words, relative reduction in the film thickness of the panel plating layer causes such problems as deteriorated reliability of the through-hole conductor and increased conductive resistance of the through-hole conductor.